As very large scale integrated (VLSI) circuits tend to get more complex, there is a need to switch more output driver circuits and internal latches at a faster rate in order to increase their performance. This increase in the switching rate results in an increase in the amount of electrical noise associated therewith.
Various techniques have been utilized in the art to minimize the level of noise associated with the increase in the magnitude of the switching rate. One known technique for reducing the level of noise is to incorporate discrete capacitors as a decoupling capacitance between associated pins of the power supply voltage. Generally, the discrete capacitor, which is mounted at a distance from the semiconductor chip is electrically coupled thereto by a plurality of power wiring lines or large power buses. These power wiring lines typically represent long inductance paths. Moreover, as the switching rate of the current flowing in the plurality of wiring lines increases, a voltage drop develops there across. The voltage drop is viewed as unwanted power distribution noise.
One technique of minimizing the inductance path is to move the discrete capacitor as close as possible to the semiconductor chip. However, in view of either the layout of the wiring lines associated with the semiconductor chip or the physical dimensions of the discrete capacitor, the discrete capacitor cannot be positioned such that there is no voltage drop or noise. Additionally, the discrete capacitors used for this purpose are usually high-frequency, low-inductance capacitors which increase the cost associated with the use of this technique. The noise level created by the increase in the rate of current switching limits the performance and the number of simultaneously switchable VLSI circuits.
Consequently, there is a need for a technique which reduces the noise associated with the increase in the rate of current switching and which minimizes the inductance paths and the cost associated therewith.
Narken et al. "Low Capacitive Via Path Through High Dielectric Constant Material", IBM TDB Vol. 22, No. 12, pp. 5330-1 (May 1980), describes a decoupling capacitor located in a multilayer structure directly below a chip with wires extending to the dielectric material of the capacitors. The arrangement is intended to minimize the inductance of the structure.
Lussow "Internal Capacitors and Resistors for Multilayer Ceramic Modules" IBM TDB Vol. 20, No. 9, pp. 3436-7 (February 1978), describes a multilayer ceramic module with capacitors incorporated within the green sheet structure.
In these prior art chip carriers, it is a problem to provide capacitors with relatively high values located near the chips and to provide ultra-low inductance connections between the chips and the capacitors. High-performance packages will require on-module decoupling capacitors to suppress simultaneous switching noise. Such capacitors should have minimum inductance, ideally, zero inductance. For this reason EP-A No. 0 083 405 discloses a ceramic carrier for any number of VLSI chips, the carrier including a built-in capacitor structure. There are aligned connector lines extending in opposite directions to eliminate out magnetic flux induced by currents in the leads to the capacitor. The capacitor comprises multiple segments which are located within the body of the carrier and which are connected such that they are adapted to easy mechanical or laser deletion for altering the capacitance of the capacitor or for removing defects after fabrication.
Instead of using ceramic carriers, a packaging technique using silicon as a multi-chip carrier is disclosed by Spielberger et al., "Silicon-on-Silicon Packaging", IEEE Transactions on Components, "Hybrids and Manufacturing Technology", Vol. CHMT-7, No. 2, pp. 193-196, (June 1984). The multiple integrated circuit chips are flip-chip or face-down bonded which involves physically locating and bonding the pads of the circuit chips to corresponding pads of the wiring layers provided on the interconnection carrier. This packaging technique offers considerable advantages. Since the photoengraving technology used in the interconnection carrier and on the chips is identical, very high packaging densities are achieved, with minimum area requirements for interconnections. Furthermore, low-cost packaging can be achieved, since the carrier utilizes conventional integrated processes, and semiconductor material defects are tolerable as there are no active devices. However, there is the option of using the carrier for active devices.
Continuing this packaging technology, the PCT application No. WO 86/02 490 (which corresponds to U.S. Pat. No. 4,675,717) discloses integrated circuit packages comprising integrated circuit chips mounted and electrically connected to a power supply distribution wiring and a chip interconnection signal wiring formed on the surface of a semiconductor interconnection carrier in which a power supply decoupling capacitor is implemented. The silicon carrier is highly doped to render it relatively conductive. A substantially planar metallization layer is formed overlaying the top-surface of the carrier. A dielectric layer is under laying a major portion of the top surface metallization layer. This portion of the metallization layer forms one plate of the carrier-size decoupling capacitor. Additionally, a continuous metallization layer is formed on the bottom surface of the carrier. The conductive carrier itself and the bottom surface layer form the other plate of this capacitor. Whenever electrical connection is between a pad on the chip and the upper surface layer, the carrier-size capacitor is also connected to the chip in low-inductance fashion for effective decoupling.
These presently known and available packages have been developed mainly for bipolar chip applications. In the meantime, industry has switched from bipolar to CMOS technology on a large scale. CMOS technology offers new possibilities, that means, very high density, low power consumption, and integratability of full processor units on one chip. The available packages are optimized for multi-chip processor units for high-power consumption and high-performance bipolar chips. These packages have to support high DC-currents on power lines and even on signal lines.
The CMOS VLSI technique puts new requirements on the package. The CMOS VLSI chips require very high current surges on the power supplies. Therefore, a new and CMOS optimized package concept is required.
The invention as claimed overcomes the problems associated with the requirement of reducing the noise caused by the increase in the rate of current switching. The invention provides an improved electronic package in which semiconductor chips are mounted on a semiconductor interconnection carrier and in which decoupling capacitors are an integrated part of the power distribution system.
The chip carrier proposed is specially designed for fast and high-density CMOS applications. In order to support high-speed CMOS chips, there is a decoupling capacitor integrated in the carrier. The wiring on the chip carrier is laid out for lowest capacity and minimized impedance.